NASA’s High Performance Spaceflight Computing project aims to dramatically improve the computing power of spacecraft. Missions need processors that can withstand the harsh space environment, so they use chips developed years ago that are hardy and reliable. But upgraded chips are needed to enable the development of autonomous spacecraft, accelerate the rate of scientific discovery through faster data analysis, and support astronauts on missions to the Moon and Mars.
“Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing,” said Eugene Schwanbeck, program element manager in NASA’s Game Changing Development program at the agency’s Langley Research Center, in Hampton, Virginia. “NASA’s commitment to advancing spaceflight computing is a triumph of technical achievement and collaboration.”
The centerpiece of the High Performance Spaceflight Computing project is a new radiation-hardened, high-performance processor, designed to provide up to 100 times the computational capacity of current spaceflight computers while enduring a barrage of challenges in space. NASA’s Jet Propulsion Laboratory in Southern California has been conducting various tests that replicate those challenges.
“We are putting these new chips through the wringer by carrying out radiation, thermal, and shock tests while also evaluating their performance through a rigorous functional test campaign,” said Jim Butler, High Performance Space Computing project manager at JPL.
The processor must endure myriad tests to prove it can survive the rigors of spaceflight, including electromagnetic radiation and extreme temperature swings, both of which can degrade electronics. High-energy particles from the Sun and interstellar space can cause errors that send a spacecraft into “safe mode,” where nonessential operations are shut down until mission operators resolve the issue.
There are also unique challenges associated with landing on planetary bodies. “To simulate real-world performance, we are using high-fidelity landing scenarios from real NASA missions that would typically require power-intensive hardware to process huge volumes of landing-sensor data,” said Butler. “This is an exciting time for us to be working on hardware that will enable NASA’s next giant leaps.”
Testing at JPL, which began in February, will continue for several months. Results have been promising: The processor is working as designed and indications show it operating at 500 times the performance of the radiation-hardened chips currently in use. In a symbolic milestone, the team sent an email at the start of testing with the subject line “Hello Universe” — a nod to the test message that was popular in early computer development.
Built by Microchip Technology Inc., headquartered in Chandler, Arizona, the High Performance Spaceflight Computing processor is being developed by the company and JPL through a commercial partnership. Samples have been provided to early access partners in the broader defense and commercial aerospace industry. The technology will enable autonomous spacecraft to use artificial intelligence to respond in real time to complex situations and environments where human input isn’t possible. It will help deep space missions analyze, store, and transmit troves of data to Earth, accelerating the rate of science discoveries. It could also support future human missions to the Moon and Mars.
Known as a system-on-a-chip (or SoC), the processor can fit in the palm of a hand and includes all the key components of a computer, such as central processing units, computational offloads, advanced networking units, memory, and input/output interfaces. Compact and energy-efficient, SoCs are commonly found in smartphones and tablets. But only the SoCs JPL is testing are built to survive for years, millions (or even billions) of miles from the nearest repair technician, enduring conditions that even the toughest home user couldn’t replicate.
Once certified for spaceflight, NASA will incorporate the chip into the computing hardware for many of the agency’s Earth orbiters, rovers exploring planetary surfaces, crewed habitats, and deep-space missions. The technology will be adapted by Microchip for Earth-based industries too, such as aviation and automotive manufacturing. The versatility of High Performance Spaceflight Computing supports NASA’s continued advancements in space exploration while providing transformative tools for numerous fields on Earth.
The project is managed by the Space Technology Mission Directorate’s Game Changing Development (GCD) program based at NASA Langley. The GCD program and JPL, a division of Caltech in Pasadena, California, led the end-to-end maturation of the High Performance Spaceflight Computing technology by developing mission requirements, funding industry studies, and guiding the project life cycle to delivery. NASA JPL selected Microchip as a partner in 2022, and the company funded its own research and development of the processor.
For more information about the High Performance Spaceflight Computing project, visit:
News Media Contacts
Ian J. O’Neill
Jet Propulsion Laboratory, Pasadena, Calif.
818-354-2649
ian.j.oneill@jpl.nasa.gov
Jasmine Hopkins
NASA Headquarters, Washington
321-432-4624
jasmine.s.hopkins@nasa.gov
2026-031
